1. Field of the Invention
The present invention relates to packaging substrates and fabrication methods thereof, and, more particularly, to a packaging substrate for carrying a semiconductor chip and a fabrication method thereof.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are developed towards multi-function and high performance. Packaging substrates used for carrying semiconductor chips are required to have reduced thicknesses to meet the miniaturization requirement of semiconductor packages.
However, decreasing thickness of packaging substrates increases problems in fabrication. For example, such a packaging substrate can easily get stuck when it is moved across various processing stations, thus adversely affecting the fabrication efficiency. Further, such a packaging substrate can easily warp or crack due to its reduced thickness, which accordingly leads to an undesired product yield.
Therefore, small leadless packages (SLPs) are provided. In particular, a carrier is added to one side of a packaging substrate during fabrication and removed after the molding process, thereby meeting miniaturization requirement, facilitating mass production and reducing fabrication cost.
Referring to FIG. 1A, a packaging substrate 1 used in a small leadless package has a carrier 10 having a first copper lamination layer 101 and a second copper lamination layer 102 formed on the first copper lamination layer 101, and a base body 1a disposed on the second copper lamination layer 102. The first and second copper lamination layers 101, 102 are laminated together through vacuum lamination.
The base body 1a has a first circuit layer 11 formed on the second copper lamination layer 102 through electroplating, a dielectric layer 12 formed on the second copper lamination layer 102 and the first circuit layer 11, a second circuit layer 13 formed on the dielectric layer 12 through electroplating, a plurality of conductive vias 14 formed in the dielectric layer 12 through electroplating for electrically connecting the first and second circuit layers 11, 13, and an protection layer 15 formed on the dielectric layer 12 and the second circuit layer 13.
Referring to FIG. 1B, the first copper lamination layer 101 is separated and removed from the second copper lamination layer 102 through a vacuum breaking process so as to remove the carrier 10.
However, since the first circuit layer 11 is made of an electroplated copper material, the bonding force between the first circuit layer 11 (electroplated copper) and the second copper lamination layer 102 (laminated copper) is greater than the bonding force between the first circuit layer 11 (electroplated copper) and the dielectric layer 12 (non-metal material). As such, when the first copper lamination layer 101 is removed along with an edge portion of the second copper lamination layer 102a, a portion of the first circuit layer 11a is also removed due to the great bonding force between the second copper lamination layer 102a and the first circuit layer 11a, thereby damaging the first circuit layer 11 and reducing the product yield.
Therefore, there is a need to provide a packaging substrate and a fabrication method thereof so as to overcome the above-described drawbacks.